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DataFlash® Serial Flash Architecture


Serial DataFlash

Atmel and Digi-Key introduce the World's Most Flexible Serial Interface Flash Family

Atmel’s new Serial DataFlash® family offers system designers a flexible and advanced Serial Flash architecture. With its uniform page erase size as small as 256 bytes and its ability to perform a completely self-contained read-modify-write operation, the DataFlash allows system designers to fully optimize system performance and memory efficiency to reduce their total BOM cost. DataFlash devices feature a common command interface and an 8-pin compatible footprint for easy migration from 1-Mbit to 64-Mbit densities.

The Atmel-programmed unique ID number, user programmable sector protection, and user programmable permanent sector locking along with the page erase capability and integrated, fully independent SRAM buffers enable system designers to utilize a single, very low pin-count memory device for all of their nonvolatile memory needs. With the current 2.7V and 2.5V minimum voltage options and 1.65V minimum versions in development, DataFlash devices align well with current and future ASIC and SoC technologies. The DataFlash family was developed with flexibility, performance, and ease-of-use in mind and can help drive your system cost reduction initiatives.

  • Features
  • Diagram

Features

  • DataFlash® Page Erase Serial Flash
  • 1-Mbit to 64-Mbit densities
  • Granular Memory Array
  • Small Page Array Architecture
    • Individually erasable pages
    • Page sizes of 256/264, 512/528, or 1024/1056 bytes
  • On-Chip, Independently Accessible SRAM Buffers
  • True EEPROM emulation (self-contained read-modify-write)
  • Serial SRAM buffers easily used as a system resource
    • Permanently turn any combination of sectors into ROM
  • Advanced Protection and Security Features
  • Individual sector protection
  • Individual sector lockdown
    • Permanently turn any combination of sectors into ROM
  • 128-byte OTP security register
    • Atmel-programmed unique ID in every device
    • 64 bytes of user programmable OTP
  • High Endurance
  • 100,000 cycles per page minimum
    • Allows more updates than block erase architectures
  • High Speed
  • 66MHz+ SPI compatible
  • JEDEC Manufacturer and Device ID Standard

Diagram

Serial DataFlash Diagram




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