Virtex-5

The World's First 65nm FPGA

Built on the revolutionary ExpressFabric™ architecture, the Xilinx Virtex™-5 family is the ultimate system integration platform. With the industry’s highest performance, ultimate connectivity, optimized power, and lowest system cost, you can design next-generation systems for wired/wireless networking, audio/video, storage/server and other markets with maximum productivity.

Digi-Key Part Number	Number of I/O	Number of Logic Blocks	Usable Gates	Package	Temp	Voltage
122-1527-ND	480	6,480	85K	1136-FBGA	0°C to +85°C	1.00 V
122-1558-ND	220	2,400	30K	324-FBGA	0°C to +85°C	1.00 V
122-1562-ND	220	3,600	50K	324-FBGA	0°C to +85°C	1.00 V
122-1560-ND	360	2,400	30K	665-FBGA	0°C to +85°C	1.00 V
122-1565-ND	360	3,600	50K	665-FBGA	0°C to +85°C	1.00 V
122-1559-ND	400	2,400	30K	676-FBGA	0°C to +85°C	1.00 V
122-1563-ND	440	3,600	50K	676-FBGA	0°C to +85°C	1.00 V
122-1557-ND	440	8,640	110K	676-FBGA	0°C to +85°C	1.00 V
122-1564-ND	480	3,600	50K	1136-FBGA	0°C to +85°C	1.00 V
122-1561-ND	560	3,600	50K	1153-FBGA	0°C to +85°C	1.00 V
122-1566-ND	360	2,720	35K	665-FBGA	0°C to +85°C	1.00 V
122-1567-ND	480	4,080	50K	1136-FBGA	0°C to +85°C	1.00 V
122-1568-ND	360	4,080	50K	665-FBGA	0°C to +85°C	1.00 V

HW-V5-ML501-UNI-G Evaluation Platform

Spec Sheet

Data Sheet

User Guide

What's New in Virtex-5 FPGAs


	•	Virtex-5 and Virtex-4 comparison
	•	1.0V, 65nm triple-oxide process increases performance and lowers power consumption
	•	ExpressFabric Architecture uses Real 6-input LUTs for fewer logic levels and ultra-fast diagonal routing for reduced net delays
	•	More Flexible Clock Management Tile combines new PLL for precise clock phase control and jitter filtering with DCM for versatile clock synthesis
	•	Enhanced 36 Kbit Block RAM logic and ECC for building larger arrays includes power-saving circuits switch off unused memory
	•	1.25 Gbps SelectIO™ structures simplify high-bandwidth parallel interfaces with enhanced ChipSync™ technology
	•	Low power 100 Mbps–3.2 Gbps RocketIO™ GTP transceivers implement serial protocols
	•	550 MHz DSP48E slices with 25 x 18 MACs enable single-precision floating point math using 50% fewer resources
	•	System Monitor simplifies system management and diagnostics with built-in analog-to-digital converter
	•	Second-generation sparse chevron packaging improves signal integrity while reducing system cost
	•	Enhanced device configuration reduces cost with support for commodity flash memory