CY14B101x and CY14B256x

Fast Static RAM with a Nonvolatile Element in Each Memory Cell

Introducing Cypress's nonvolatile random access memory that integrates Quantum Trap nonvolatile elements into high-performance SRAM memory cells. The memory array is accessed identically to conventional SRAM. On power-up RECALL the nonvolatile elements set the state of the SRAM. The nvSRAM may then be read or written without altering the nonvolatile elements. RECALL may also be initiated upon command. The parallel transfer of all data from the nonvolatile elements to SRAM requires a maximum of only 20 microseconds to complete. If data is written to the SRAM, a STORE operation will set the state of the nonvolatile elements in parallel from the SRAM. Depending on the device selected STORE can be initiated automatically on power-down, by hardware command, or by software command. 15 msec is required to save all SRAM data (zero system time during power down AutoStore).

Digi-Key p/n	Cypress p/n	Memory Size	Speed	Interface	Package
428-2028-5-ND	CY14B101L-SP35XC	1M (128K x 8)	35nS	Parallel	48-SSOP
428-2029-5-ND	CY14B101L-SZ35XC	1M (128K x 8)	35nS	Parallel	32-SOIC
428-2027-5-ND	CY14B101K-SP35XC	1M (128K x 8)	35nS	Parallel	48-SSOP
428-2031-5-ND	CY14B256L-SP35XC	256K (32K x 8)	35nS	Parallel	48-SSOP
428-2032-5-ND	CY14B256L-SZ35XC	256K (32K x 8)	35nS	Parallel	32-SOIC
428-2030-5-ND	CY14B256K-SP35XC	256K (32K x 8)	35nS	Parallel	48-SSOP

Features   • Reliable nonvolatile storage without battery   • Unlimited read, write and recall cycles   • 500,000 store cycles to nonvolatile elements   • 20 Year data retention with better than 5 FITs reliability   • Automatic write protect   • Directly replaces SRAM, battery-backed SRAM, EPROM or EEPROM   • SRAM pin-outs and timings Applications   • RAID controllers   • Set-top boxes   • Copiers   • POS terminals   • Industrial automation   • Data communications   • Multi-function printers   • Single board computers Benefits   • RoHS compliant   • No batteries or contacts to fail   • No data loss from electrical noise or undershoot   • Faster read/write capability   • Smaller footprint than competing technologies   • No socketing or secondary manufacturing steps required   • No power monitoring required   • Eliminates EEPROM limitations   • Symmetrical read/write accesses to 25 nsec   • Can store full array on power-down using zero system time