- Overview
- Features & Applications
- Diagram
- Specifications
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Overview
This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 900MHz. Fabricated in core CMOS process, the ADC11DV200 may be operated from a single 1.8V power supply. The ADC11DV200 achieves approximately 10.06 effective bits at Nyquist and consumes just 280mW at 170MSPS in CMOS mode and 450W at 200MSPS in LVDS mode. The power consumption can be scaled down further by reducing sampling rates. |
Features
- Single 1.8V power supply operation
- Power scaling with clock frequency
- Internal sample-and-hold
- Internal or external reference
- Power down mode
- Offset binary or 2's complement output data format
- LVDS or CMOS output signals
- 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
- Clock Duty Cycle Stabilizer
- IF Sampling Bandwidth > 900MHz
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Applications
- Digital Predistortion (DPD)
- Wireless Communications Infrastructure
- Medical Imaging
- Portable Instrumentation
- Digital Video
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Block Diagram
 |
Resolution |
11 Bits |
Conversion Rate |
200 MSPS |
ENOB |
10.06 bits (typ) @Fin=70MHz |
SNR |
62.5 dBFS (typ) @Fin=70MHz |
SINAD |
62.3 dBFS (typ) @Fin=70MHz |
SFDR |
82 dBFS (typ) @Fin=70MHz |
LVDS Power |
450 mW (typ) @Fs=200 MSPS |
CMOS Power |
280 mW (typ) @Fs=170 MSPS |
Operating Temperature Range |
–40°C to +85°C |
| Available in Tape & Reel (TR-ND), Cut Tape (CT-ND), and custom Digi-Reel® (DKR-ND) |
National Semiconductor Part Number |
Digi-Key Part Number |
Sampling Rate (Per Second) |
Number of Bits |
Package/Case |
ADC11DV200CISQE/NOPB |
|
200M |
11 |
60-LLP |
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