- Input data rate > 12 Gb/s typical
- Data dependent jitter < 20 ps
- Maximum input clock frequency > 8 GHz typical
- Random clock jitter < 0.8 ps RMS
- Multi-level inputs, accepts LVPECL, CML, LVDS
- Low skew 1:8 CML outputs, < 25 ps max
- Differential CML outputs, 400 mV peak-to-peak, typical
- Operating range: VCC = 2.375 V to 3.6 V,
GND = 0 V
- Internal input termination resistors, 50-ohm
- VREFAC Reference output
- -40C to +85C Ambient operating temperature
|
- Clock distribution for SONET, gigabit ethernet and fiber channel
- Network routers and multiprocessor synchronous clock distribution
|